Project Information c:\classes\ee290\pldprobs\codeconv.rpt
MAX+plus II Compiler Report File
Version 6.2 06/12/96
Compiled: 04/03/97 22:13:07
Copyright (c) 1996 by Altera Corporation. All rights reserved. This text
contains proprietary, confidential information of Altera Corporation, and
may be used, copied, and/or disclosed only pursuant to the terms of a
valid software license agreement with Altera Corporation. This copyright
notice must be retained as part of this text at all times.
***** Project compilation was successful
4-bit Code Converter Example
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
codeconv EP610ILC-10 4 4 0 4 0 25 %
User Pins: 4 4 0
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
***** Logic for device 'codeconv' compiled without errors.
Device: EP610ILC-10
Turbo: ON
Security: OFF
R R
E E
S S
E E
R R
V G V V V
E g N C C g E
D 3 D C C 0 D
-----------------------_
/ 4 3 2 1 28 27 26 |
| |
RESERVED | 5 25 | RESERVED
| |
RESERVED | 6 24 | RESERVED
| |
RESERVED | 7 23 | RESERVED
| |
b3 | 8 EP610ILC-10 22 | RESERVED
| |
b2 | 9 21 | RESERVED
| |
b1 | 10 20 | RESERVED
| |
N.C. | 11 19 | N.C.
|_ 12 13 14 15 16 17 18 _|
------------------------
b g G G G g R
0 2 N N N 1 E
D D D S
E
R
V
E
D
N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
** RESOURCE USAGE **
Logic Array Block Logic Cells I/O Pins
A: LC1 - LC8 0/ 8( 0%) 0/ 8( 0%)
B: LC9 - LC16 4/ 8( 50%) 4/ 8( 50%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 4/16 ( 25%)
Total logic cells used: 4/16 ( 25%)
Total input pins required: 4
Total output pins required: 4
Total bidirectional pins required: 0
Total logic cells required: 4
Total flipflops required: 0
Synthesized logic cells: 0/ 16 ( 0%)
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
** INPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
27 - - INPUT 0 0 4 0 g0
17 - - INPUT 0 0 3 0 g1
13 - - INPUT 0 0 3 0 g2
3 - - INPUT 0 0 3 0 g3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
** OUTPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
12 16 B OUTPUT 4 0 0 0 b0
10 15 B OUTPUT 2 0 0 0 b1
9 14 B OUTPUT 4 0 0 0 b2
8 13 B OUTPUT 3 0 0 0 b3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
** LOGIC CELL INTERCONNECTIONS **
Logic cells placed in LAB 'B'
+------- LC16 b0
| +----- LC15 b1
| | +--- LC14 b2
| | | +- LC13 b3
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | |
LC16 -> - - - - | <-- b0
LC15 -> - - - - | <-- b1
LC14 -> - - - - | <-- b2
LC13 -> - - - - | <-- b3
Pin
27 -> @ @ @ @ | <-- g0
17 -> @ - @ @ | <-- g1
13 -> @ @ @ - | <-- g2
3 -> @ - @ @ | <-- g3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
@ = The input pin or logic cell feeds the logic cell (or LAB) using direct interconnect.
- = The logic cell or pin is not an input to the logic cell (or LAB).
§
Device-Specific Information: c:\classes\ee290\pldprobs\codeconv.rpt
codeconv
** EQUATIONS **
g0 : INPUT;
g1 : INPUT;
g2 : INPUT;
g3 : INPUT;
-- Node name is 'b0'
-- Equation name is 'b0', location is LC016, type is output.
b0 = LCELL( _EQ001);
_EQ001 = g0 & g1 & g2 & g3
# !g0 & g1 & g2 & !g3
# g0 & !g1 & g2 & !g3
# !g0 & !g1 & g2 & g3
# !g0 & g1 & !g2 & g3;
-- Node name is 'b1'
-- Equation name is 'b1', location is LC015, type is output.
b1 = LCELL( _EQ002);
_EQ002 = g0 & g2;
-- Node name is 'b2'
-- Equation name is 'b2', location is LC014, type is output.
b2 = LCELL( _EQ003);
_EQ003 = g0 & g2 & g3
# !g0 & !g1 & g2;
-- Node name is 'b3'
-- Equation name is 'b3', location is LC013, type is output.
b3 = LCELL( _EQ004);
_EQ004 = !g0 & g1 & g3;
§
Project Information c:\classes\ee290\pldprobs\codeconv.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'CLASSIC' family
MINIMIZATION = full
SOFT_BUFFER_INSERTION = on
TURBO_BIT = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic I/O Cell Registers = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interface Menu Commands
-----------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 2,127K
Send comments and suggestions about this example to:
Dr. Charles S. Tritt
This page last updated 4/3/97